Digital System Design Using Verilog
Subject Code | Credits | CIE Marks | SEE Marks | Total Marks | Exam Hours |
---|---|---|---|---|---|
BEC302 | 04 | 50 | 50 | 100 | 03 |
Module 1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine- McCluskey Minimization Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
Module 2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs) (Section5.1to5.7 ofText2)
Module 3
Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip- flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
Module 4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3) Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description.(Section2.1to2.2(only Verilog) of Text3)
Module 5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to 3.4 (onlyVerilog)of Text 3) Verilog Structural description: Highlights of Structural description, Organization of structural description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)
VIMP
Very important questions serve as a crucial element in exam preparation, allowing students to focus on the most relevant content and effectively gauge their understanding. By practicing these questions, students can build confidence, enhance their knowledge, and approach their exams with a well-rounded perspective. Ultimately, mastering these key questions can make a significant difference in academic performance.
Solved MQ
Solved model question papers are a cornerstone of effective exam preparation. They not only familiarize students with the exam format but also enhance their problem-solving abilities and boost their confidence. By incorporating these papers into your study routine, you can approach your exams with a sense of preparedness and assurance. Remember, the key to success lies not just in practice, but in understanding and learning from each experience.
Lab Manual
Experiments :-
1. To simplify the given Boolean expressions and realize using Verilog program
2. To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3. To realize 4-bit ALU using Verilog program.
4. To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa
b)Binary to excess3 and vice versa
5. To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6. To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7. To realize using Verilog Behavioral description:
Flip-flops:
a)JK type
b)SR type
c)T type and
d)D type
8. To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.